1. Field of the Invention
The present invention relates to a sample/hold circuit, and more particularly to a circuit arrangement of a sample/hold circuit.
2. Discussion of the Related Art
As known, the sample/hold circuit receives a voltage level at the input terminal thereof at a specific timing, and outputs the received voltage level in the form of a hold voltage.
A typical conventional sample/hold circuit is shown in FIG. 4. As shown, the sample/hold circuit is made up of buffer circuits B1 and B2 for impedance conversion at the input and the output terminals Vi and Vo, switching elements S1 and S2 for connection and disconnection of a signal, and capacitors 5 and 6 for holding a received voltage level.
The buffer circuit B1 has a non-inverting input terminal, an inverting input terminal, and an output terminal. The non-inverting input terminal of the buffer circuit B1 is connected to the input terminal Vi. The inverting input terminal of the buffer circuit B1 is connected to the output terminal of the buffer circuit B1 per se in a feedback fashion. The output terminal of the buffer circuit B1 is connected through the switching element S1 to the capacitor 5, and further to the non-inverting input terminal of the buffer circuit B2 and the capacitor 6, through the switching element S2. The output terminal of the buffer circuit B2 is connected to the output terminal Vo, and to the inverting input terminal of the buffer circuit B2 per se in a feedback fashion. The switching elements S1 and S2 are turned on and off under control signals L1 and L2 outputted from a control circuit 4.
A timing chart showing an operation of the conventional sample/hold circuit arranged as shown in FIG. 4 is shown in FIG. 5.
In a sampling mode of the sample/hold circuit, the switching element S1 is turned on by the control signal L1, while the switching element S2 is turned off by the control signal L2. In the sampling mode, the sample/hold circuit receives an input voltage.
In a holding mode, the switching element S1 is turned off, while the switching element S2 is turned on, under control of the control circuit 4. In the holding mode, the sample/hold circuit holds the received voltage in the capacitor 5, and o outputs the held voltage to the output terminal Vo by way of the buffer circuit B2.
In the sampling mode, the voltage level at the input terminal Vi is applied to the capacitor 5 as it is. The output voltage is retained in the capacitor 6 of which the capacitance is remarkably smaller than that of the capacitor 5. The voltage at the input terminal Vi varies as indicated by dotter lines (waveform at Vo in FIG. 5) when it is inputted to the capacitor 5.
The sample/hold circuit shown in FIG. 4 can be realized by a simple circuit arrangement. However, the sample/hold circuit merely holds the voltage in the capacitors 5 and 6, after receiving the voltage from the input terminal Vi. Because of this, the sample/hold circuit suffers from some problems.
Firstly, the hold voltage gradually varies as in the segment t1 in FIG. 5. This is due to the leakage of current from the capacitor 5 or 6. Secondly, the hold voltage abruptly varies as in the segment t2 in FIG. 5 or the voltage at the output terminal Vo is greatly deviated from the hold voltage as received. This problem arises from noise generated in the power supply line or the circuit. Particularly where the hold time is long under the condition of high temperature or much noise is present, the deviation or the drift of the hold voltage is appreciable. Thirdly, when the sample/hold circuit operates in the holding mode, the capacitor 6 is coupled in parallel with the capacitor 5. In this state, the hold voltage across the capacitor 5 is sheared to the capacitor 6, so that the hold voltage varies.
An attempt to increase the capacitances of the capacitors 5 and 6 succeeds in suppressing the voltage variation caused by the leak current from the capacitors 5 and 6 and the abrupt variation of the voltage by the noise voltage. However when the capacitors 5 and 6 are excessively increased in capacitance, it is impossible to integrate the sample/hold circuit containing those capacitors into a single chip. In other words, the capacitors must be incorporated, as external components, into a single chip of the integrated circuit. This runs counter to the current design trend to reduce the number of external components.
In the conventional sample/hold circuit, when the power source is turned off, the capacitors are discharged, so that the held voltage varies. For this reason, the sample/hold circuit must be operated for the sample/hold purposes every time the power source thereof is turned on. This hinders a quick start-up of the system.